ASIC and FPGA Product Development
ASIC and FPGA product development programs are among the most schedule-sensitive and cost-constrained programs in engineering. A missed tapeout window adds six months and significant non-recurring cost. A post-silicon surprise that requires a re-spin adds twelve. Managing these programs requires a PM who understands the engineering milestones that actually matter — not just the calendar dates on a Gantt chart — and who can coordinate design, verification, foundry, packaging, firmware, and qualification teams toward a shared delivery model.
Where NPI Programs Break Down
Product requirements that continue to evolve after RTL architecture is committed force design rework that multiplies the cost and schedule impact of every late change. Requirements freeze is a program milestone, not a formality.
Silicon validation and production qualification activities that are not planned before tapeout consistently underscope the test infrastructure, fixture development, and regulatory certification timelines required for production release.
Tapeout window commitments made by engineering without business awareness, or business commitments made without engineering input on tape-in readiness, produce the same outcome: missed foundry slots and six-month schedule penalties.
Post-silicon validation is not the same as bench testing. Full-system validation against production firmware, hardware-software integration, environmental testing, and regulatory certification require dedicated planning before silicon arrives.
What NPI Program Management Delivers
System requirements review, requirements traceability setup, architecture decision records, and requirements change control — ensuring design starts from a locked baseline, not a moving target.
PM-facilitated architecture lock review, pre-implementation design reviews, and peer review cadence management — with review packages prepared, distributed, and action items tracked to closure.
Milestone tracking against engineering states — RTL freeze, simulation coverage thresholds, formal verification closure — rather than elapsed time. Verification planning managed as a first-class program workstream.
Foundry interface management, tape-in package assembly, DRC/LVS sign-off tracking, timing closure verification, and tapeout readiness review — coordinating all tape-in deliverables to meet the foundry window.
Bring-up plan management, validation environment readiness, test coverage tracking, bug triage coordination, and re-spin decision governance — managing the post-silicon phase as a structured program, not an open-ended lab exercise.
ATE program handoff, production test coverage review, regulatory certification timeline management, supplier qualification tracking, and production ramp milestone governance through first customer shipment.
NPI Program Lifecycle — Six-Phase Governance Model
System requirements lock, architecture decision records, make-vs-buy decisions, foundry selection, and IP sourcing. Program baseline established before design begins.
Architecture lock review, RTL partitioning, verification planning, IP integration planning, and design team onboarding. All downstream assumptions validated at entry.
RTL development milestone tracking, simulation coverage gates, formal verification closure, timing analysis checkpoints, and DFT planning. Scope controlled through change request process.
Final sign-off tracking, tape-in package coordination, foundry communication, mask set management, and post-tapeout validation environment preparation.
Bring-up coordination, validation test coverage tracking, hardware-software integration governance, bug priority management, and re-spin decision support.
ATE handoff, production test coverage, regulatory certification management, supplier qualification, and production ramp milestone governance.
Program Types
- Full-custom ASIC development programs — digital, analog, mixed-signal
- SoC development programs with multiple IP blocks and foundry PDK management
- FPGA-to-ASIC migration programs requiring parallel validation strategies
- Chiplet and multi-die system development programs
- MEMS and photonic integrated circuit development programs
- Defense and aerospace ASIC programs with MIL-SPEC qualification requirements
- University-industry ASIC programs with NSERC, IRAP, or NRC funding
Related Services and Resources
Managing an ASIC or FPGA product development program?
PMOVA provides senior program managers who understand semiconductor NPI — from requirements lock and architecture review through tapeout coordination, silicon validation, and production qualification.